Configuration Controller Generator

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General overview

The graphic user interface of the tool presents as follows:


How it works?

  • Configuration Controller Generator (CCG) is a mixture of two tools:
    • VHDL-Post Processing Tool (Simulation Tool, also called CCG Functional Block)
      • The tool permits to carry out a functional simulation of the dynamic description resulting from a manual or automatic partition using standard VHDL simulators. For the user convenience it has been built as a part of CCG
    • Configuration Controller Generator (also called CCG Technology Dependent Block)
      • The tool is able to generate C code that may be later compiled in order to provide a software controller for the dynamic implementation of the system. Moreover, it is able to generate the hardware, synthesizable VHDL description of the configuration controller. At the end, the generated VHDL files may be merged together in the top level file for the functional simulation (with the cooperation with VHDL-Post Processing Tool) or for the hardware implementation of the system
  • For the user convenience these two tools pervades each other increasing their functionality
  • Both of the tools are requiring the same input set
  • Both of the tools may start to generate their outputs from the same menu
Functional Block
  • Main features of the tool:
    • Permits to carry out a functional validation for the results of the partitioning process
    • Identify the active dynamic modules at any given time
    • Analyse the effect of unloaded d_modules on the whole design
  • Dynamic simulation process based on the DCS (Dynamic Circuit Switch) techniques proposed by Lysaght et al
  • Activation/Deactivation of dynamic modules emulated by means of isolation switches
  • Generates a functional description of the configuration controller (Schedule Control Module – SCM) and the isolation switches
  • Dynamic simulation fully compatible with static verification (same set of stimuli)
  • Permits the user to select the files that are going to be included in the top level file
    • To ease this task a number of help buttons has been designed, that choose the software (SW) or hardware (HW) version of the file that is going to be generated
    • SW version is used for functional simulation
    • HW version is used for implementation
  • Inputs:
    • VHDL files containing:
      • dynamic modules
      • interface elements (cut entities)
      • static part
    • DCF file generated by the manual partitioning tools
  • Outputs:
    • Functional description (VHDL or C) of the configuration controller (FCC)
    • Bidirectional switches used to isolate d_modules
    • Dynamic modules with added switches description
    • Top entity including d_modules, switches, FCC and static parts
    • Model simulation *.do file
Technology Dependent Block
  • Manages all the reconfiguration processes affecting the Dynamic Modules generated by the System Scheduler
  • Can generate either a hardware version (VHDL synthesisable description) or a software version (description in C language) for the controller
  • Detailed description of the controller requires information from the Back-End tools
  • Manages all the signal saving processes
  • The architecture of the software controller is general enough to permit the interface with any kind of microprocessor/ microcontroller
  • Inputs:
    • VHDL files containing:
      • dynamic modules
      • interface elements (cut entities)
      • static part
    • DCF file generated by the manual partitioning tools
  • Outputs:
  • Physical Configuration Controller in C code
  • Reconf Interface, that is a collection of:
    • Event Detector
    • Sequential Scheduler
    • Physical Configuration Controller in VHDL code
    • Physical Interface

More information

Please head to MIXDES’2005 talk.


The tool was part of the Reconf 2 Work package 4 (WP4) research.

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