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Summary

RECONF 2: Design Methodology and Environment for Dynamic RECONFigurable FPGA Funded under 5th FWP (Fifth Framework Programme) (IST–2001–341016)

Overall project summary: The aim of RECONF2 was to allow implementation of adaptive system architectures by developing a complete design environment to take full benefits of dynamic reconfigurable FPGAs (D_FPGAs).

Total project duration: III.2002 – XII.2004

Contact person: Marie Joseph Berard or Philippe Butel, MBDA France

My role

Software researcher at  Work Package 4: Development of the Two Front-End tools:

• Manual Partitioning Tool, a dynamic reconfiguration management (system partitioning) tool
• Configuration Controller Generator, a data management tool

I was working within the project from II.2003 to XII.2004 (1 year 11 months)

More information

Project objectives

• Complex SRAM based FPGA are very expensive
• Detailed analysis of system functional blocks allows to consider:
  • Permanent blocks (Static)
  • Occasional blocks (Dynamic)
• All the blocks implemented simultaneously into the FPGA result in chip:
  • Over dimension
  • Over consumption
  • Over cost
• There are different modes of reconfiguration:
  • Global, static
  • Partial, static
  • Partial, Dynamic: Reconfigure some areas of the FPGA while the rest of the design is still running
• The challenge: Sequentially download the configuration of the dynamic blocks while maintaining, until the switch to the new configuration, the operation of the static blocks
• RECONF 2 addresses Partial Dynamic Reconfiguration
  • Implementation possible with Xilinx and Atmel technologies
  • Few experiments, mostly research
  • No methodology, no specific tools, no verification available
  • Difficult to implement, relies on modular backend, few usage

Project organization

Project outputs

• Provide a complete design methodology
  • Relies on existing tools for simulation and synthesis
  • Provide verification methodology for reliable implementation
  • Remains as technology independent as possible
• Provide Front-end design tools (WP4 outputs)
  • Partitioning of a classic static design
  • Specifying reconfiguration scheduling and others dynamic constraints
  • Provide netlists for dynamic verification through classic static VHDL simulation tools
• Back-end design tools
• Use diversified types of application for demonstrating the efficiency of the resulting tools
• Disseminate, promote and explain the benefits of the resulting tools:
  • Easy applications upgrade
  • Low power consumption

Please head to MIXDES’2005 talk.