Research

Publications

Conferences

  • Kamil Kędzierski, Miquel Moreto, Francisco J. Cazorla and Mateo Valero. Adapting Cache Partitioning Algorithms to Pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS), April 19-23, 2010. ATLANTA (Georgia) USA.
    slideshow, pdf
  • Kamil Kędzierski, Miquel Moreto, “Pseudo-LRU based Cache Partitioning Algorithms”, Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 12-16, 2009, Raleigh, (North Carolina) USA.
    pdf
  • K. Kędzierski, J.M. Moreno, J. Cabestany, “Front–End Tools for Dynamic Reconfiguration in FPGA Devices”, Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), June 2005, pages 121 – 126, Kraków, Poland
    slideshow, pdf

Workshops

  • Kamil Kędzierski, Francisco Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero. . Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, June 2010, Saint-Malo, France
    pdf
  • Kamil Kędzierski, Francisco J. Cazorla, Mateo Valero, “Analysis of Multithreading Capabilities of Current High–Performance Processors”, XVII Jornadas de Paralelismo, September 18 – 20, 2006, pages 55 – 61, Albacete, Spain
    slideshow, pdf
  • Kamil Kędzierski, Francisco J. Cazorla and Mateo Valero, “Analysis of Simultaneous Multithreading Implementations in Current High–Performance Processors”, ACACES Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, Poster Session, July 26th, 2006, Proceedings of the poster abstracts, pages 113–116, Academia Press, ISBN 90 382 0981 9, L’Aquila, Italy
    pdf, poster
  • K. Kędzierski, J.M. Moreno, J. Scandaliaris, A. Napieralski, “Functional Configuration Controller as a Part of Simulation Tool for Dynamically Reconfigurable Devices”, Proceedings of the III Jornadas de Computación Reconfigurable y Aplicaciones (JCRA), June 2003, pages 11 – 18, Madrid, Spain

Reports

  • Kamil Kędzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero, “ReCaC: Power and Performance Aware Reconfigurable Cache for CMPs”, Technical Report, UPC-DAC-RR-CAP-2008-40, Barcelona, 2008
  • K. Kędzierski, J.M. Moreno, J. Cabestany, “Constraints Editor, Technical Requirement Specification”, UPC (2004)
  • K. Kędzierski, J.M. Moreno, J. Cabestany, “Post–Processing Tool. Technical Requirement Specification”, UPC (2004)
  • K. Kędzierski, J.M. Moreno, J. Cabestany, “Configuration Controller Generator. Technical Requirement Specification”, UPC (2004)

Theses

  • Kamil Kędzierski, “Development of a Simulation Tool for Dynamically Reconfigurable Devices”, MSc Thesis, Politechnika Łódzka, Łódź, Poland
  • K. Kędzierski, “Functional Configuration Controller as a Part of Simulation Tool for Dynamically Reconfigurable Devices”, final report of the Socrates/Erasmus exchange program, Technical University of Catalonia, Barcelona, Spain

Patent

  • K. Kędzierski, J. M. Moreno–Arostegui, J. Cabestany “Procedure for Manual Partitioning for Dynamic Reconfiguration in FPGA Devices”, UPC, 2005, withdrawn

Disclaimer: The publications on this page are subject to ACM, IEEE or other copyrights as noted in papers.


Reviews

Journals

  • since 2013
    Embedded Hardware Design (Microprocessors and Microsystems), MICPRO
  • since 2011
    Journal of Computer Networks and Communications, JCNC
  • since 2008
    IEEE Micro Journal
  • since 2008
    IEEE Transactions on Computers, ToC

Conferences

  • since 2011
    ACM International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS
  • since 2010
    ACM International Conference on Computing Frontiers, CF
  • since 2009
    International Conference on Computer-Aided Design, ICCAD
  • since 2009
    International Conference on Supercomputing, ICS
  • since 2009
    International Symposium on Low Power Electronics and Design, ISLPED
  • since 2008
    International Conference on Architecture of Computing Systems, ARCS
  • since 2008
    Euromicro Conference on Digital System Design, DSD
  • since 2007
    International Symposium on Computer Architecture, ISCA
  • since 2007
    International Conference for High Performance Computing, Networking, Storage and Analysis, SuperComputing, SC
  • since 2007
    International Conference on Parallel Architectures and Compilation Techniques, PACT
  • since 2007
    Asia-Pacific Computer Systems Architecture Conference, ACSAC
  • since 2006
    IEEE International Parallel & Distributed Processing Symposium, IPDPS
  • since 2006
    IEEE International Symposium on High–Performance Computer Architecture, HPCA
  • since 2006
    IEEE International Conference on Computer Design, ICCD

Talks (short list)

Invited Talks

18.X.2011
K. Kędzierski „Last Level Shared Cache in the Era of Power and Complexity Constrained Designs”, IRISA (The Research Institute in Computer Science and Random Systems) / INRIA (The National Institute for Research in Computer Science and Control), Rennes, France
chair: André Seznec
26.IV.2006
J. Jasiewicz, K. Kędzierski „Transformación política, cultural y social de Polonia hacia la democracia” (Political, cultural and social transformation of Poland towards democracy), a lecture given in the framework of BA course “Processos socials” (Social Processes) at the Universidad de Barcelona, Spain
chair: Elisabet Almeda

Conferences

19.VI.2010
Kamil Kędzierski, Francisco Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero. . Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, Saint-Malo, France
21.IV.2010
Kamil Kędzierski, Miquel Moreto, Francisco J. Cazorla and Mateo Valero. Adapting Cache Partitioning Algorithms to Pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS) April 19-23, 2010. ATLANTA (Georgia) USA.
18.IX.2006
Kamil Kędzierski, Francisco J. Cazorla, Mateo Valero, “Analysis of Multithreading Capabilities of Current High–Performance Processors”, XVII Jornadas de Paralelismo, September 18 – 20, 2006, Albacete, Spain
26.VII.2006
Kamil Kędzierski, Francisco J. Cazorla and Mateo Valero, “Analysis of Simultaneous Multithreading Implementations in Current High–Performance Processors”, ACACES Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, Poster Session, L’Aquila, Italy
23.VI.2005
Kamil Kędzierski, “Front–End Tools for Dynamic Reconfiguration in FPGA Devices”, presentation of the paper at the 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES’2005)
30.VI.2003
K. Kędzierski, “Development of a Simulation Tool for Dynamically Reconfigurable Programmable Devices”, Socrates/Erasmus exchange final presentation