Employment

I am a CPU Design Engineer at ARM Ltd. based in Cambridge, UK.

Contact

Before joining ARM, I was an Expert Development Engineer at INRIA in France. I worked on Sequential Accelerators in Future Manycore Processors, exploring in particular the importance of power and reliability issues. I also focused on performance, power and reliability modeling in manycore processors, including variable voltage and frequency scenario (DVFS). I was a software developer of a parallel simulator for hardware devices (work under DAL project).

My previous work focused on power and complexity in the last level shared cache of Chip-Multiprocessor architectures. I developed solutions for power-aware cache partitioning, analyzed interactions between applications in shared resources and proposed cache partitioning for industrial implementations (work under HPC 5, SOW on POWER5 and HiPEAC projects).

I also developed the Front-End CAD tools supporting dynamic reconfiguration in FPGA devices with extensive GUI. These tools, based on MFC libraries in C++, consisted of VHDL parser of the input files, drag-n-drop support for creating output files, and VHDL code generation such that the output and input files had the same functionality (work under Reconf 2 project).

In my work, I aim to combine solid reasoning with creativity. One could say I do not leave if statement without the final else in the source code as I believe the reliability of the product is the main long-term value.

since XII.2013

ARM_logo.svg

CPU Design Engineer, ARM Ltd., UK
I.2012 – XI.2013
(1 year 11 months)INRIA Rennes (Institut national de recherche en informatique et en automatique, The National Institute for Research in Computer Science and Control)
Expert Development Engineer at INRIA Rennes (Institut national de recherche en informatique et en automatique, The National Institute for Research in Computer Science and Control), France

Project: Defying Amdahl’s Law – DAL.

I.2006 – XII.2011
(6 years)
Several roles in parallel at:

  • Barcelona Supercomputing Center (BSC), Spain
  • Technical University of Catalonia (UPC), Spain
  • IBM T.J. Watson Research Center, Yorktown, NY, USA

Roles overlap due to collaboration between the institutions.

I.2010 – XII.2011
(2 years)bsc_logo
Resident Student at Barcelona Supercomputing Center (BSC), SpainFunds: Scientific scholarship funded by the Barcelona Supercomputing Center

Project: Computación de Altas Prestaciones V

I.2006 – XII.2009
(4 years)bsc_logo
Associate Resident Student at Barcelona Supercomputing Center (BSC), SpainPart of the PhD research.Funds: Scientific scholarship funded by the Spanish Ministry of Education

Projects: Computación de Altas Prestaciones V, SOW on POWER5, HiPEAC

V.2005 – XII.2009
(4 years 8 months)upc_logo
Research Fellow at the Department of Computer Architecture, Technical University of Catalonia (UPC), SpainFunds: Scientific scholarship funded by the Spanish Ministry of Education, Scientific scholarship funded by the Catalan Government, Scholarship funded by the Technical University of Catalonia

Projects: Computación de Altas Prestaciones V, SOW on POWER5, HiPEAC

X – XII.2009
(3 months)ibm_logo
Visiting Researcher at the IBM T.J. Watson Research Center, Yorktown, NY, USAFunds: Spanish Ministry of Education grant

Project: SOW on POWER5

VIII – XI.2007
(4 months)ibm_logo
Visiting Researcher at the IBM T.J. Watson Research Center, Yorktown, NY, USAFunds: HiPEAC grant

Project: SOW on POWER5

I.2005 – IV.2005
(4 months)upc_logo
Patent Writer. The Patent title: “Procedure for Manual Partitioning for Dynamic Reconfiguration in FPGA Devices”, Technical University of Catalonia, Spain

Project: Reconf 2

II.2003 – XII.2004
(1 year 11 months)upc_logo
Software Developer in the RECONF 2 European Project (IST–2001–341016),
http://www.reconf.org at the Technical University of Catalonia (UPC), SpainProject: RECONF 2
VII.2002 – I.2003
(7 months)logo_philip_morris_polska
Intern at the Philip Morris Polska, S.A., Technical Documentation Department, Kraków, Poland
V 2002 – VII 2002
(3 months)logo_philips
Intern at the Philips Lighting Pabianice S.A. Company, Automotive Department, Pabianice, Poland
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